1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly, to an LCD array substrate in which a thin film transistor region is arranged at a center side portion of a unit pixel and data line and gate line are substituted for source electrode and gate electrode, and a fabrication method thereof.
2. Discussion of the Related Art
Generally, a liquid crystal display operates by the optical anisotropy and polarization of a liquid crystal material therein. Since the liquid crystal material includes liquid crystal molecules each having a thin and long structure, the liquid crystal material has a directionality according to the arrangement of the liquid crystal molecules. Hence, the arrangement direction of the liquid crystal molecules can be controlled by applying an external electric field to the liquid crystal. As the arrangement direction of the liquid crystal molecules are changed by applying an electric field, light polarization caused by the optical anisotropy of the liquid crystal material is modulated to display image information.
Liquid crystal material can be classified into positive (+) liquid crystal having a positive dielectric anisotropy and negative (−) liquid crystal having a negative dielectric anisotropy depending on its electrical properties. Liquid crystal molecules having a positive dielectric anisotropy are arranged such that their long axes are parallel with the direction of an applied electric field, and liquid crystal molecules having a negative dielectric anisotropy are arranged such that their long axes are normal to the direction of an applied electric field.
Nowadays, an active matrix LCD in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix configuration are widely being used because of their high resolution and superior moving picture reproducing capability. Hereinafter, a structure of a liquid crystal panel that is a main element of the LCD will be reviewed.
FIG. 1 is a partial exploded perspective view of a general LCD. Referring to FIG. 1, a general color LCD includes an upper substrate 5 and a lower substrate 22. The upper substrate 5 includes a black matrix 6, a color filter 7 having sub-color filters of red (R), green (G), and blue (B), and a transparent common electrode 18 formed on the color filter 7. The lower substrate 22 includes pixel regions (P), pixel electrodes 17 formed on the pixel regions (P), and an array interconnection line including switching elements (T). Between the upper substrate 5 and the lower substrate 22, a liquid crystal layer 15 is interposed as described above.
The lower substrate 22 is called an “array substrate.” On the lower substrate 22, a plurality of thin film transistors functioning as switching elements are arranged in a matrix configuration, and a gate line 13 and a data line 15 are formed to cross the plurality of thin film transistors. The pixel regions (P) are defined by the gate lines 13 and the data lines 15 crossed with the gate lines 13. The pixel electrode 17 formed on the pixel region (P) is made of a transparent conductive material, such as indium-tin-oxide (ITO), having superior light transmittance. The LCD 11 constructed as above displays images when liquid crystal molecules of the liquid crystal layer 14 on the pixel electrode 17 are aligned by a signal voltage applied from the thin film transistor to control the amount of light passing through the liquid crystal layer 14.
Also, the LCD array substrate 22 constructed as above is formed by a deposition process, a photolithography process (hereinafter referred to as a “photo-process”), an etch process and the like. The photo-process utilizes a principle in which when photoresist (PR) is exposed to light, a chemical reaction occurs to change the property of the PR. In the photo-process, light is selectively irradiated onto the PR through a mask of a desired pattern, thereby forming the same pattern as the pattern of the mask. The photo-process includes a PR coating step in which a photoresist corresponding a general picture film is coated on, an exposure step in which light is selectively irradiated onto the PR using a mask, and a developing step in which the exposed portion of the PR is removed to form a pattern.
FIG. 2 is a partially magnified plan view of pixels of a related art LCD array substrate. Referring to FIG. 2, a pixel region (P) is defined by a pair of gate lines 13 and a pair of data lines 15 crossed with the pair of gate lines 13. At a cross point of the data line 15 and the gate line 13, a thin film transistor (T) having gate electrode 31, source electrode 33, and drain electrode 35 is formed. The source electrode 33 and the drain electrode 35 are spaced apart by a predetermined interval from each other on the gate electrode 31, and an active channel (semiconductor layer) 37a is exposed between the source electrode 33 and the drain electrode 35.
As a scanning pulse is applied to the gate electrode 31 of the thin film transistor (T) and the voltage of the gate electrode 31 is increased, the thin film transistor (T) is turned ON. At this time, if a liquid crystal driving voltage is applied to the liquid crystal material via drain and source regions of the thin film transistor (T) from the data line 13, pixel capacitance, which includes liquid crystal capacitance and storage capacitance, is charged. By repeating the above operation, a voltage corresponding to a video signal for every frame time is applied repeatedly to the pixel capacitance of the front surface of the LCD panel. Finally, if an arbitrary pixel is switched by the thin film transistor, the switched pixel passes light from the lower light source.
FIGS. 3A to 3D are plan and sectional views schematically showing a process to fabricate the LCD array substrate of FIG. 2. In FIGS. 3A to 3D, the sectional views are taken along line I-I′ of FIG. 2. Here, while FIG. 3 shows that the array substrate is formed by a process requiring four masks, the array substrate may be formed by a process requiring five masks. If the array substrate is formed by a process using five masks, the semiconductor layer 37 may not be formed below the data line 15.
FIG. 3A corresponds to a first mask step in which metal, such as copper or the like, is deposited and patterned to form the gate line 13 and the gate electrode 31. Next, a gate insulating film 32 and an amorphous semiconductor (silicon) layer 37′, an impurity-doped amorphous semiconductor (silicon) layer 36′, and a conductive metal layer 33′ are deposited on the substrate on which the gate line 13 and the like are already formed.
FIG. 3B corresponds to a second mask step in which the conductive metal layer 33′ is patterned to form the data line 15 crossing with the gate line 13, the source electrode 33 is protruding perpendicularly from the data line 15 by a predetermined area, and the drain electrode 35 spaced apart by a predetermined interval from the source electrode 33. Next, the exposed impurity-doped amorphous silicon 36′ is etched using the patterned metal layer as an etch stopper such that the amorphous silicon layer 37′ is exposed between the data line and the drain electrode.
FIG. 3C corresponds to a third mask step in which a passivation layer 41 of an electrically insulating material is formed on the substrate on which the data line 15 and the like are formed. The passivation layer 41 is patterned to form drain contact holes 43 for the drain electrode 35. Portions of the passivation layer 41 are also removed from the pixel region (P) except for upper portions of the gate electrode 31, the source electrode 33, the drain electrode 35, upper portions of the gate line 13, and upper portions of the data line 15. While the passivation layer 41 is patterned, the semiconductor layer 37 and the gate insulating film 32 below the passivation layer are patterned at the same time. Accordingly, below the patterned passivation layer 41, the semiconductor layer 37 is etched in the same pattern as the passivation layer 41.
FIG. 3D corresponds to a fourth mask step in which the pixel electrode 17 contacting the drain electrode 35 through the drain contact holes 43 is formed.
Thus, the related art array substrate is formed by the foregoing process and the screen size of the array substrate is greater than that of the exposure mask used in the photo-process. Hence, during the exposure step, the screen of the array substrate is divided into a plurality of shots and is repeatedly exposed, and such a repeated process is further generalized as the large-sized LCDs are mass-produced in recent years. However, limitations in the preciseness of the exposure equipment causes reduced picture quality of the LCD by the stitch failure that the misalignment between the shots occurs.
Also, in the case of forming the data lines defining the pixel region crossing with the gate line, the source electrode and the drain electrode spaced apart by a certain interval from the source electrode by patterning the conductive metal layer using the mask step of FIG. 3B, the limitation in the preciseness of the exposure equipment or the like causes the mask not to be precisely accorded with an intended specification and, thus, to be deviated from the correct position by some degree. As a result, an overlay failure where the gate electrode and the source/drain electrode are not regularly overlapped every pixel region occurs so that picture quality of the LCD is reduced.
With reference to FIG. 4, the phenomenon where the picture quality is reduced in the LCD is described in more detail. FIGS. 4A to 4C illustrate stitch/overlay failures according to the contact area of the source/drain electrode with the gate electrode.
In FIGS. 4A to 4C, the stitch failure is a problem occurring when the alignment degree between shots on the same layer is not constant, and the overlay failure is a problem occurring due to a misalignment of the mask between different layers. However, since the result of the stitch failure is the same as that of the misalignment failure, their descriptions are made with reference to the same drawings of FIGS. 4B and 4C.
FIG. 4A is plan view and sectional view of a thin film transistor region where a stitch/overlay failure does not occur.
Referring to FIG. 4A, parasitic capacitances Cgs and Cgd are generated due to the existence of the overlapping regions between the gate electrode 31 and the source electrode 33 and between the gate electrode 31 and the drain electrode 35. The parasitic capacitance changes the liquid crystal voltage by ΔV when the thin film transistor is turned on, so that a voltage difference is caused between the initially applied voltage and a voltage applied to the liquid crystal. The ΔV is approximately expressed by equation 1 below:
                              Δ          ⁢                                          ⁢          V                =                                            C              gd                                                      C                gd                            +                              C                LC                            +                              C                ST                                              ⁢          Δ          ⁢                                          ⁢                      V            g                                              (        1        )            where, Cgd is a parasitic capacitance, CLC is a liquid crystal capacitance, CST is a storage capacitance, and ΔVg is a voltage different between gate voltages in ON and OFF states, Vgh and Vgl.
Thus, due to the voltage difference ΔV, a phenomenon where the picture undesirably becomes dark and bright during display, (i.e., flicker) occurs. The flicker is overcome by moving the common voltage (Vcom) from the center of the data signal voltage by ΔV such that a direct current (dc) component is deleted while the LCD is operated. In other words, if ΔV is generated in the respective pixels and is constant, the flicker can be overcome by moving the common voltage a constant amount.
As shown in FIG. 4A, if the parasitic capacitances with respect to the respective thin film transistor regions in a plurality of pixels are constant, this problem can be solved. However, if the parasitic capacitances with respect to the respective thin film transistor regions in a plurality of pixels are not constant due to a stitch and/or overlay failure, the flicker cannot be overcome by moving the common voltage (Vcom) a constant amount.
FIGS. 4B and 4C are plan view and sectional view of a thin film transistor region where the stitch/overlay failure occurs.
If the stitch failure (i.e., misalignment between shots occurs) or the overlay failure (i.e., misalignment of masks occurs between different layers), a difference occurs between the overlapping region between the gate electrode 31 and the source electrode 33 and the overlapping region between the gate electrode 31 and the drain electrode 35. As a result, a difference between the parasitic capacitances Cgs and Cgd is caused. In other words, as shown in FIG. 4B, in a state that the side of the drain electrode 35 is misaligned toward the side of the source electrode 33, the capacitor Cgd between the gate and the drain becomes large. Meanwhile, as shown in FIG. 4C, in a state that the side of the source electrode 33 is misaligned toward the drain electrode 35, the capacitance Cgd between the gate and the drain becomes small.
As aforementioned, if a difference between the parasitic capacitances occurs for every pixel region, which represents that the capacitance Cgd is varied in the ΔV, the value of the ΔV becomes not constant. Accordingly, it is impossible to prevent the flicker by only moving the common voltage (Vcom) a constant amount as with the related art. Therefore, the array substrate produced by the related art fabrication method of the LCD array substrate has a difficulty in overcoming a picture imbalance in an LCD caused by the stitch and/or overlay failure.